1. Field of the Invention
The present invention relates, in general, to a method of fabricating a self-aligned top gate organic transistor. More particularly, the invention relates to a self-aligned deposition of a gate electrode forming part of an organic field effect transistor.
2. Related Technology
Transistors can be divided into two main types: bipolar junction transistors and field-effect transistors. Both types share a common structure comprising three electrodes with a semi-conductive material disposed therebetween in a channel region. The three electrodes of a bipolar junction transistor are known as the emitter, collector, and base, whereas in a field-effect transistor the three electrodes are known as the source, drain, and gate. Bipolar junction transistors may be described as current-operated devices as the current between the emitter and collector is controlled by the current flowing between the base and emitter. In contrast, field-effect transistors may be described as voltage-operated devices as the current flowing between source and drain is controlled by the voltage between the gate and the source.
Transistors can also be classified as p-type and n-type according to whether they comprise semi-conductive material which conducts positive charge carriers (holes) or negative charge carriers (electrons) respectively. The semi-conductive material may be selected according to its ability to accept, conduct, and donate charge. The ability of the semi-conductive material to accept, conduct, and donate holes or electrons can be enhanced by doping the material. The material used for the source and drain electrodes can also be selected according to its ability to accept and inject holes or electrodes.
For example, a p-type transistor device can be formed by selecting a semi-conductive material that is efficient at accepting, conducting, and donating holes and selecting a material for the source and drain electrodes that is efficient at injecting and accepting holes from the semi-conductive material. Good energy-level matching of the Fermi-level in the electrodes with the highest occupied molecular orbital (HOMO) level of the semi-conductive material can enhance hole injection and acceptance. In contrast, an n-type transistor device can be formed by selecting a semi-conductive material which is efficient at accepting, conducting, and donating electrons, and selecting a material for the source and drain electrodes which is efficient at injecting electrons into, and accepting electrons from, the semi-conductive material. Good energy-level matching of the Fermi-level in the electrodes with the lowest occupied molecular orbital (LUMO) level of the semi-conductive material can enhance electron injection and acceptance.
Transistors can be formed by depositing the components in thin films to form a thin film transistor (TFT). When an organic material is used as the semi-conductive material in such a device, it is known as an organic thin film transistor (OTFT).
Various arrangements for organic thin film transistors are known. One such device is an insulated gate field-effect transistor which comprises source and drain electrodes with a semi-conductive material disposed therebetween in a channel region, a gate electrode disposed adjacent the semi-conductive material and a layer of insulting material disposed between the gate electrode and the semi-conductive material in the channel region.
OTFTs may be manufactured by low-cost, low-temperature methods such as solution processing. Moreover, OTFTs are compatible with flexible plastic substrates, offering the prospect of large-scale manufacture of OTFTs on flexible substrates in a roll-to-roll process.
It is known to provide a gate electrode at the top of an organic thin film transistor to form a so-called top-gate organic thin film transistor. An example of a top-gate organic thin film transistor can be found in U.S. Pat. No. 6,734,505.
In such an architecture source and drain electrodes are deposited on a substrate and spaced apart to define a channel region therebetween. A layer of an organic semiconductor material is deposited in the channel region to connect the source and drain electrodes and may extend at least partially over the source and drain electrodes. An insulating layer of dielectric material is deposited over the organic semiconductor material and may also extend at least partially over the source and drain electrodes. A gate electrode is deposited over the insulating layer and located over the channel region.
The substrate may be rigid or flexible. Rigid substrates may be selected from glass or silicon and flexible substrates may comprise thin glass or plastics such as poly(ethylene terephthalate) (PET), poly(ethylene-naphthalate) (PEN), polycarbonate, and polyimide.
The organic semiconductive material may be made solution processable through the use of a suitable solvent. Exemplary solvents include mono- or poly-alkylbenzenes such as toluene and xylene; tetralin; and chloroform. Preferred solution deposition techniques include spin-coating and ink jet printing. Other solution deposition techniques include dip-coating, roll printing and screen printing.
Preferred organic semiconductor materials include small molecules such as optionally substituted pentacene; optionally substituted polymers such as polyarylenes, in particular polyfluorenes and polythiophenes; and oligomers. Blends of materials, including blends of different material types (e.g. a polymer and small molecule blend) may be used.
For a p-channel OTFT, preferably the source and drain electrodes comprise a high workfunction material, preferably a metal, with a workfunction of greater than 3.5 eV, for example gold, platinum, palladium, molybdenum, tungsten, or chromium. More preferably, the metal has a workfunction in the range of from 4.5 to 5.5 eV. Other suitable compounds, alloys and oxides such as molybdenum trioxide and indium tin oxide may also be used. The source and drain electrodes may be deposited by thermal evaporation and patterned using standard photolithography and lift off techniques as are known in the art.
Alternatively, conductive polymers may be deposited as the source and drain electrodes. An example of such a conductive polymer is poly(ethylene dioxythiophene) (PEDOT) although other conductive polymers are known in the art. Such conductive polymers may be deposited from solution using, for example, spin coating or ink jet printing techniques and other solution deposition techniques discussed above.
For an n-channel OTFT, preferably the source and drain electrodes comprise a material, for example a metal having a workfunction of less than 3.5 eV such as calcium or barium or a thin layer of metal compound, in particular an oxide or fluoride of an alkali or alkali earth metal for example lithium fluoride, barium fluoride and barium oxide. Alternatively, conductive polymers may be deposited as the source and drain electrodes.
The length of the channel defined between the source and drain electrodes may be up to 500 microns, but preferably the length is less than 200 microns, more preferably less than 100 microns, most preferably less than 20 microns.
The gate electrode can be selected from a wide range of conducting materials for example a metal (e.g. gold) or metal compound (e.g. indium tin oxide). Alternatively, conductive polymers may be deposited as the gate electrode. Such conductive polymers may be deposited from solution using, for example, spin coating or ink jet printing techniques and other solution deposition techniques discussed above.
Thicknesses of the gate electrode, source and drain electrodes may be in the region of 5 mm-200 nm, although typically 50 nm as measured by Atomic Force Microscopy (AFM), for example.
The insulating layer comprises a dielectric material selected from insulating materials having a high resistivity. The dielectric constant, k, of the dielectric is typically around 2-3 although materials with a high value of k are desirable because the capacitance achievable for an OTFT is directly proportional to k, and the drain current ID is directly proportional to the capacitance. Thus, in order to achieve high drain currents with low operational voltages, OTFTs with thin dielectric layers in the channel region are preferred.
The dielectric material may be organic or inorganic. Preferred inorganic materials include SiO2, SiNx and spin-on-glass (SOG). Preferred organic materials are generally polymers and include insulating polymers such as poly vinylalcohol (PVA), polyvinylpyrrolidine (PVP), acrylates such as polymethylmethacrylate (PMMA) and benzocyclobutanes (BCBs) available from Dow Corning. The insulating layer may be formed from a blend of materials or comprise a multi-layered structure.
The dielectric material may be deposited by thermal evaporation, vacuum processing, or lamination techniques as are known in the art. Alternatively, the dielectric material may be deposited from solution using, for example, spin coating or ink jet printing techniques and other solution deposition techniques discussed above.
In a top-gate architecture, the dielectric material is deposited from solution onto the organic semiconductor and should not result in dissolution of the organic semiconductor. Techniques to avoid such dissolution include: use of orthogonal solvents, that is use of a solvent for deposition of the uppermost layer that does not dissolve the underlying layer; and crosslinking of the underlying layer.
The thickness of the insulating layer is preferably less than 2 micrometres, more preferably less than 500 nm.
Other layers may be included in the device architecture. For example, a self assembled monolayer (SAM) may be deposited on the gate, source or drain electrodes, substrate, insulating layer, and organic semiconductor material to promote crystallity, reduce contact resistance, repair surface characteristics, and promote adhesion where required. In particular, the dielectric surface in the channel region may be provided with a monolayer comprising a binding region and an organic region to improve device performance, e.g. by improving the organic semiconductor's morphology (in particular polymer alignment and crystallinity) and covering charge traps, in particular for a high k dielectric surface. Exemplary materials for such a monolayer include chloro- or alkoxy-silanes with long alkyl chains, e.g. octadecyltrichlorosilane. Similarly, the source and drain electrodes may be provided with a SAM to improve the contact between the organic semiconductor and the electrodes. For example, gold source and drain electrodes may be provided with a SAM comprising a thiol binding group and a group for improving the contact which may be a group having a high dipole moment; a dopant; or a conjugated moiety.
In order to fabricate an organic electronic circuit such as an active matrix display backplane it is necessary to pattern the core active components of an organic transistor such as the organic semiconductor and dielectric layers. Patterning allows each organic transistor to be isolated from each other and avoids the presence of a continuous organic semiconductor film which can introduce cross talk between organic transistors in the electronic circuit compromising circuit performance. Organic semiconductor and dielectric patterning is also required to open up vias to allow upper and lower metallization layers to make contact.
One approach to patterning is to pattern the organic semiconductor layer or dielectric layers directly using targeted ink jet printing techniques. However targeting droplets of active material using a ink jet print head is challenging and due in part to differences of morphology between different ink formulations and process conditions, the performance of ink jet printed organic transistors is typically below that of corresponding organic transistors in which the layers have been coated by other techniques.
Poor alignment between conducting layers can cause a problem of capacitance caused by overlap between a source and/or drain electrodes and a gate electrode. The presence of capacitance can have a significant impact in terms of circuit response time and current leakage, particularly where there are a large number of devices in parallel such as a large number of switch transistors on a data line. In addressing the problem, it is noted that some overlap is preferable to a gap which, in introducing a much increased contact resistance, would have a much worse effect on RC constant.